1. Field of the Invention This invention concerns an output circuit for a semiconductor device. More particularly, this invention concerns an output circuit which can transmit a signal at high speed when a number of semiconductor devices are connected and used together.
2. Description of the Prior Art
Conventionally, to supply a synthesized signal of output signals from several semiconductor devices to a following semiconductor device, a wired OR circuit composed of several semiconductor devices, each having an open drain type output circuit as shown in FIG.1, is used. The open drain type output circuit of FIG i includes a MOS transistor 1 having a gate electrode being supplied with an input signal Si, and a drain electrode directly connected to an output terminal 2.
As shown in FIG.2, in order to connect several of these semiconductor devices 3 in parallel, the open drain type output terminals 2 of each semiconductor device 3 are connected together to construct a wired OR circuit. A resistor R is connected between a power source terminal 4 and an output terminal 20 in order to make an output signal So a high level when all the output signals from the semiconductor devices 3 are at a high level and the output impedance of the respective semiconductor device 3 is high. The output signal So is used as an input signal for a following semiconductor device 5.
As shown in FIG.2, a wired OR circuit can be made by interconnecting output terminals 2 to which the drains of the MOS transistors 1 of the individual semiconductor devices 3 are directly connected, and also connecting the resistor R between the output terminal 20 and the power source terminal 4. In this construction, when any one of MOS transistors 1 in the semiconductor devices 3 becomes conductive, the potential of the output signal So is reduced to a partial voltage of the power source voltage Vcc in accordance with the ratio of the resistance value of the resistor R and the ON resistance of MOS transistor 1 which is conductive.
FIG.3 shows the relationship between the input signal Si to the MOS transistor 1 of any of the semiconductor devices 3 and the change of the potential at the output terminal 20 in FIG.2. In the condition when all the input signals Si of semiconductor devices 3 are low level, all the MOS transistors 1 are non-conductive, and output signal So is pulled-up to the power source voltage Vcc due to the resistor R.
Here, when an input signal Si of any one of semiconductor devices 3 becomes high level, the output signal So reduces to the voltage described above. Also, when the input signals Si of all semiconductor devices 3 become low level, the potential of the output signal So increases to the power source voltage Vcc in accordance with a time constant RC determined by the resistance value of the resistor R and the capacitance C of the output terminal 20, so that all MOS transistors 1 become non-conductive. The capacitance C is a total of the capacitances due to the semiconductors 3, the following semiconductor device 5 and the wiring for the output terminal 20, etc.
In a system as shown in FIG.2, when any one of the output MOS transistors 1 of the semiconductor devices 3 becomes conductive, a current flows through the power source terminal 4, the resistor R, the MOS transistor I, which is in the conductive state, and the ground terminal 6. Generally, the value of the resistor R is set from several k.OMEGA. to several 10s of k.OMEGA. in order to reduce the consumption current. When the system becomes large-scale, the number of semiconductor devices 3 which make up the wired OR circuit is increased and the semiconductor devices which are supplied with the output signal So as their input is increased. Thus, the wiring for the output signal So also increases, and the capacitance C of the output terminal becomes larger.
Here, if the resistance value of the resistor R and the capacitance C are respectively assumed to be 10 k.OMEGA. and 50 PF, the time T taken for the output signal So to rise from a low level to the power source voltage Vcc becomes the large value of T=RC=10 k.OMEGA..times.50 PF=500 nsec. In order to make this T a small value, since the capacitance 0 is determined when the system is determined, the resistance R must be reduced. However, in the case where the resistor R has small resistance value, the current flowing through the resistor R increases, and the power consumption is increased.
Furthermore, when the current flowing through the resistor R is large, the falling time of the output signal So from a high level to a low level becomes large, because the relatively large current flows as a charge current to the capacitance 0 when the discharge current flows through the MOS transistor 1, which is conductive. In addition, since the level of the output signal is determined by the ratio of the resistor R and the ON resistance of the MOS transistor 1, the low level of &he output signal So become relatively high.
In this way, when using the semiconductor devices with the conventional open drain type output terminal, if those output terminals were connected to construct a wired OR circuit and a resistor R is connected between those output terminals and the power source terminal, there is a problem in that, the higher the value of the resistor R, the slower the rising time of &he output signal, and the lower the resistance value of the resistor R, the greater the consumption current and the slower the falling time of the output signal.